[llvm] 7313d7d - [AArch64][v8.3a] Add missing imp-defs on RETA*.

[Ahmed Bougacha via llvm-commits]

Author: Ahmed Bougacha
Date: 2019-11-13T10:38:11-08:00
New Revision: 7313d7d6188a0ea1cebe3aa5ec27d53f4ccc1286

URL: https://github.com/llvm/llvm-project/commit/7313d7d6188a0ea1cebe3aa5ec27d53f4ccc1286
DIFF: https://github.com/llvm/llvm-project/commit/7313d7d6188a0ea1cebe3aa5ec27d53f4ccc1286.diff

LOG: [AArch64][v8.3a] Add missing imp-defs on RETA*.

RETA always implicitly uses LR, unlike RET which merely has an
alias that defaults it to LR.
Additionally, RETA implicitly uses SP as well, which it uses as
a discriminator to authenticate LR.

This isn't usually noticeable, because RET_ReallyLR is used in most
of the backend.  However, the post-RA scheduler, if enabled, will
cause miscompiles if the imp-uses are missing.

While there, fix a typo in the lone affected testcase.

Added: 
    llvm/test/CodeGen/AArch64/branch-target-enforcement.mir

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrFormats.td

Removed: 
    llvm/test/CodeGen/AArch64/branch-target-enforcment.mir


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 7317b15990d9..17f5277af9e0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1427,6 +1427,7 @@ class AuthOneOperand<bits<3> opc, bits<1> M, string asm>
   let Inst{9-5} = Rn;
 }
 
+let Uses = [LR,SP] in
 class AuthReturn<bits<3> op, bits<1> M, string asm>
   : AuthBase<M, (outs), (ins), asm, "", []> {
   let Inst{24} = 0;

diff  --git a/llvm/test/CodeGen/AArch64/branch-target-enforcment.mir b/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
similarity index 98%
rename from llvm/test/CodeGen/AArch64/branch-target-enforcment.mir
rename to llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
index 5db503ddcee9..e0eff1e2de8b 100644
--- a/llvm/test/CodeGen/AArch64/branch-target-enforcment.mir
+++ b/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
@@ -142,7 +142,7 @@ body:             |
     INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
     $w0 = ORRWrs $wzr, $wzr, 0
     early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load 8 from %stack.0)
-    RETAA implicit killed $w0
+    RETAA implicit $sp, implicit $lr, implicit killed $w0
 
 ---
 # Function starts with PACIBSP, which implicitly acts as BTI JC, so no change
@@ -166,7 +166,7 @@ body:             |
     INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
     $w0 = ORRWrs $wzr, $wzr, 0
     early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load 8 from %stack.0)
-    RETAB implicit killed $w0
+    RETAB implicit $sp, implicit $lr, implicit killed $w0
 
 ---
 # Function contains a jump table, so every target of the jump table must start