[PATCH] D68576: [PowerPC] Fix VSX clobbers of CSR registers

[Jinsong Ji via Phabricator via llvm-commits]

jsji accepted this revision.
jsji added a comment.

LGTM as well.



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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:14320
+    if (VSNum < 32)
+      return std::make_pair(PPC::VSL0 + VSNum, &PPC::VSRCRegClass);
+    return std::make_pair(PPC::V0 + VSNum - 32, &PPC::VSRCRegClass);
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Do we need to consider 32 or 64 bits regclass here? If not, maybe we should add some comments to explain?


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Comment at: test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll:3
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
----------------
Why we need `-enable-ppc-quad-precision` here?


Repository:
  rL LLVM

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