[PATCH] D70116: [RISCV] add subtargets initialized with target feature

[Kuan Hsu Chen (Zakk) via Phabricator via llvm-commits]

khchen created this revision.
khchen added reviewers: lenary, asb.
khchen added a project: LLVM.
Herald added subscribers: llvm-commits, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, dexonsmith, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, kristof.beyls, mehdi_amini.

According to https://reviews.llvm.org/D67409#1737444, previous enabling LTO patch uses a wrong approach. 
The target features have been encoded in bitcode files on a per-function basis, so clang driver does not need to pass them to LTO code generator.
So I reference ARM backend <https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/ARM/ARMTargetMachine.cpp#L252> to init subtarget if there is target features attribute.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70116

Files:
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.h
  llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll


Index: llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
+
+define float @foo(i32 %a) nounwind #0 {
+; CHECK-LABEL: foo:
+; CHECK: fcvt.s.w  ft0, a0
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+define float @foo2(i32 %a) nounwind {
+; CHECK-LABEL: foo2:
+; CHECK: call __floatsisf
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+attributes #0 = { "target-features"="+f"}
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -22,7 +22,7 @@
 namespace llvm {
 class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
-  RISCVSubtarget Subtarget;
+  mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
@@ -30,9 +30,11 @@
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
                      CodeGenOpt::Level OL, bool JIT);
 
-  const RISCVSubtarget *getSubtargetImpl(const Function &) const override {
-    return &Subtarget;
-  }
+  const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;
+  // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
+  // subtargets are per-function entities based on the target-specific
+  // attributes of each function.
+  const RISCVSubtarget *getSubtargetImpl() const = delete;
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -63,11 +63,34 @@
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
-      TLOF(std::make_unique<RISCVELFTargetObjectFile>()),
-      Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
+      TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
   initAsmInfo();
 }
 
+const RISCVSubtarget *
+RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
+  Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute FSAttr = F.getFnAttribute("target-features");
+
+  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
+                        ? CPUAttr.getValueAsString().str()
+                        : TargetCPU;
+  std::string FS = !FSAttr.hasAttribute(Attribute::None)
+                       ? FSAttr.getValueAsString().str()
+                       : TargetFS;
+  std::string Key = CPU + FS;
+  auto &I = SubtargetMap[Key];
+  if (!I) {
+    // This needs to be done before we create a new subtarget since any
+    // creation will depend on the TM and the code generation flags on the
+    // function that reside in TargetOptions.
+    resetTargetOptions(F);
+    I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, FS,
+                                         Options.MCOptions.getABIName(), *this);
+  }
+  return I.get();
+}
+
 TargetTransformInfo
 RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
   return TargetTransformInfo(RISCVTTIImpl(this, F));


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