[PATCH] D70092: [PoC][RISC-V][Vext] Unify masked and unmasked instructions

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 created this revision.
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(Not to be committed)

This is a PoC built on top of D69987 <https://reviews.llvm.org/D69987>

The goal is to halve the number of Instructions for V-ext by representing a mask as a register homogeneously: `RISCV::V0` for instructions with mask (like `vadd.vv v1, v2, v3, v0.t`) and `RISCV::NoRegister` for instructions without mask (like `vadd.vv v1, v2, v3`).

This way we don't have `VADD_VV` and `VADD_VV_T` but just `VADD_VV` with an operand that is the mask.

Changes:

- Mark the `VPRMaskAsmOperand` operand `IsOptional`, this allows it to be left empty in the instruction. If unspecified default make it be `RISCV::NoRegister` using `defaultRVVMask`.
- Actually encode `vm` in the instruction instead of making it a parameter of the class of the instruction format
- Encode, decode and print the mask operand as expected (i.e. `RISCV::V0` ↔ `v0.t` and `RISCV::NoRegister` ↔ "no mask")

Pros:

- Half the number of instructions
- Same number of operands both unmasked and masked instances of the same instruction

Cons:

- The function `RISCVAsmParser::validateInstruction` might be a bit harder to write (not done in this patch)


https://reviews.llvm.org/D70092

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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