[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

In D70000#1740485 <https://reviews.llvm.org/D70000#1740485>, @dmgreen wrote:

> It seems that this thing has been around since 2010. How come we are changing the default now, as opposed to just fixing the backends that don't support this instruction?
>
> If MIPs is the target that is failing, there should probably be a test to show it is now OK.


Yeah, it could be easy to fix those target that didn’t set as expand. But it is just hiding the problem. The key here is that, for sext_inreg for vector type, the default action should be expand instead of legal, just as what we did for sext_vector_inreg. See the test I gave on hexagon target. I write this test quickly and expose the problem. I believe we might have more potential issues as more target is added. The problem of hexagon is exactly the same as mips, as we are marking those op that didn’t have native instruction support as legal.


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https://reviews.llvm.org/D70000