[PATCH] D69326: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (3)

[Joan LLuch via Phabricator via llvm-commits]

joanlluch updated this revision to Diff 228560.
joanlluch added a comment.

Updated after D69975 <https://reviews.llvm.org/D69975> was reviewed and committed.
Now showing the codegen improvements related with this patch


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69326/new/

https://reviews.llvm.org/D69326

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll


Index: llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll
===================================================================
--- llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll
+++ llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll
@@ -6,14 +6,8 @@
 define i16 @testSimplifySetCC_2(i16 %x) {
 ; CHECK-LABEL: testSimplifySetCC_2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    clrc
-; CHECK-NEXT:    rrc r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    cmp #1, r12
+; CHECK-NEXT:    and #-64, r12
+; CHECK-NEXT:    cmp #64, r12
 ; CHECK-NEXT:    mov r2, r12
 ; CHECK-NEXT:    rra r12
 ; CHECK-NEXT:    and #1, r12
@@ -30,18 +24,9 @@
 define i16 @testSimplifySetCC_3(i16 %x) {
 ; CHECK-LABEL: testSimplifySetCC_3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    clrc
-; CHECK-NEXT:    rrc r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    tst r12
-; CHECK-NEXT:    mov r2, r13
-; CHECK-NEXT:    rra r13
-; CHECK-NEXT:    mov #1, r12
-; CHECK-NEXT:    bic r13, r12
+; CHECK-NEXT:    cmp #64, r12
+; CHECK-NEXT:    mov r2, r12
+; CHECK-NEXT:    and #1, r12
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp ugt i16 %x, 63
@@ -54,17 +39,9 @@
 define i16 @testSimplifySetCC_4(i16 %x) {
 ; CHECK-LABEL: testSimplifySetCC_4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    clrc
-; CHECK-NEXT:    rrc r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    tst r12
-; CHECK-NEXT:    mov r2, r12
-; CHECK-NEXT:    rra r12
-; CHECK-NEXT:    and #1, r12
+; CHECK-NEXT:    cmp #64, r12
+; CHECK-NEXT:    mov #1, r12
+; CHECK-NEXT:    bic r2, r12
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp ult i16 %x, 64
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3655,11 +3655,13 @@
           const APInt &AndRHSC = AndRHS->getAPIntValue();
           if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
             unsigned ShiftBits = AndRHSC.countTrailingZeros();
-            SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
-                                        DAG.getConstant(ShiftBits, dl,
-                                                        ShiftTy));
-            SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
-            return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
+            if (ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) {
+              SDValue Shift =
+                DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
+                            DAG.getConstant(ShiftBits, dl, ShiftTy));
+              SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
+              return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
+            }
           }
         }
       } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
@@ -3681,7 +3683,8 @@
         }
         NewC.lshrInPlace(ShiftBits);
         if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
-            isLegalICmpImmediate(NewC.getSExtValue())) {
+            isLegalICmpImmediate(NewC.getSExtValue()) &&
+            ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) {
           SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0,
                                       DAG.getConstant(ShiftBits, dl, ShiftTy));
           SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);


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