[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: asb, rogfer01, rkruppe, kito-cheng, khchen.
Herald added subscribers: sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

Assemble/disassemble RISC-V V extension instructions according to latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned to GNU assembler output. In this patch, there is a test case for each instruction at least.

The V register definition is just for assemble/disassemble. Its type is not important in this stage. I think it will be reviewed and modified as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.


Repository:
  rL LLVM

https://reviews.llvm.org/D69987

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/and.s
  llvm/test/MC/RISCV/rvv/clip.s
  llvm/test/MC/RISCV/rvv/compare.s
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/div.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/macc.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/minmax.s
  llvm/test/MC/RISCV/rvv/mul.s
  llvm/test/MC/RISCV/rvv/mv.s
  llvm/test/MC/RISCV/rvv/or.s
  llvm/test/MC/RISCV/rvv/others.s
  llvm/test/MC/RISCV/rvv/reduction.s
  llvm/test/MC/RISCV/rvv/shift.s
  llvm/test/MC/RISCV/rvv/sign-injection.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/sub.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/xor.s

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