[PATCH] D70000: [DAGCombine][NFC] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: efriedma, craig.topper, RKSimon, PowerPC.
Herald added subscribers: atanasyan, hiraditya, arichardson, sdardis.
Herald added a project: LLVM.

For now, we didn't set the default operation action for SIGN_EXTEND_INREG for vector type, which is 0 by default, that is legal. However, most target didn't have native instructions to support this opcode. It should be set as expand by default, as what we did for ANY_EXTEND_VECTOR_INREG.

This become critical as some target(i.e. Mips) didn't set it as expand for vector type, which will have problems as they didn't have the native instruction for it.

This patch will set the default operation action for SIGN_EXTEND_INREG for vector type as expand. And grep all the targets that specify its match pattern for vector type and make it legal.


https://reviews.llvm.org/D70000

Files:
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp


Index: llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -17,7 +17,10 @@
 static const MVT LegalW64[] =  { MVT::v128i8, MVT::v64i16,  MVT::v32i32 };
 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16,  MVT::v32i32 };
 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
-
+static const MVT InRegV64[] = { MVT::v32i8, MVT::v32i16, MVT::v16i8,
+                                MVT::v16i16, MVT::v16i32 };
+static const MVT InRegV128[] = { MVT::v64i8, MVT::v64i16, MVT::v32i8,
+                                 MVT::v32i16, MVT::v32i32 };
 
 void
 HexagonTargetLowering::initializeHVXLowering() {
@@ -58,6 +61,7 @@
   bool Use64b = Subtarget.useHVX64BOps();
   ArrayRef<MVT> LegalV = Use64b ? LegalV64 : LegalV128;
   ArrayRef<MVT> LegalW = Use64b ? LegalW64 : LegalW128;
+  ArrayRef<MVT> InRegV = Use64b ? InRegV64 : InRegV128;
   MVT ByteV = Use64b ?  MVT::v64i8 : MVT::v128i8;
   MVT ByteW = Use64b ? MVT::v128i8 : MVT::v256i8;
 
@@ -194,6 +198,9 @@
     setOperationAction(ISD::XOR,                BoolV, Legal);
   }
 
+  for (MVT T : InRegV)
+    setOperationAction(ISD::SIGN_EXTEND_INREG, T,  Legal);
+
   setTargetDAGCombine(ISD::VSELECT);
 }
 
Index: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1535,6 +1535,10 @@
   setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
   setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
 
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8,  Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
+
   // Types natively supported:
   for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
                        MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -366,6 +366,13 @@
   addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
   addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
 
+  // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8,  Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8,  Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
+
   // Some truncating stores are legal too.
   setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
   setTruncStoreAction(MVT::v4i32, MVT::v4i8,  Legal);
Index: llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -687,6 +687,7 @@
     // These operations default to expand for vector types.
     if (VT.isVector()) {
       setOperationAction(ISD::FCOPYSIGN, VT, Expand);
+      setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
       setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
       setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
       setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);


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