[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr created this revision.
dancgr added reviewers: huntergr, sdesmalen, dancgr, mgudim, amehsan, kmclaughlin.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

Added pattern matching/intrinsics for the following SVE instructions:

- saddv, uaddv
- smaxv, sminv, umaxv, uminv
- orv, eorv, andv

For some instructions (smaxv, sminv, umaxv, uminv, org, eorg, andv) the pattern wasn't implemented for i8 and i16 types.

Since i8 and i16 aren't natural types for the FPR8 and FPR16 register classes, they will need custom lowering and some other modifications in order to function properly. These changes are going to be submitted in a latter patch pending some discussion on what is the best way of implementing it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69956

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-int-reduce-pred.ll

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