[PATCH] D69849: [mips] Implement Octeon+ `saa` and `saad` instructions

[Simon Atanasyan via Phabricator via llvm-commits]

atanasyan created this revision.
atanasyan added a reviewer: Petar.Avramovic.
Herald added subscribers: jfb, jrtc27, hiraditya, arichardson, sdardis.
Herald added a project: LLVM.

`saa` and `saad` are 32-bit and 64-bit store atomic add instructions.

   
  memory[base] = memory[base] + rt
   

These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+".

      

Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69849

Files:
  llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  llvm/lib/Target/Mips/Mips.td
  llvm/lib/Target/Mips/Mips64InstrInfo.td
  llvm/lib/Target/Mips/MipsInstrFormats.td
  llvm/lib/Target/Mips/MipsInstrInfo.td
  llvm/lib/Target/Mips/MipsScheduleGeneric.td
  llvm/lib/Target/Mips/MipsScheduleP5600.td
  llvm/lib/Target/Mips/MipsSubtarget.cpp
  llvm/lib/Target/Mips/MipsSubtarget.h
  llvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt
  llvm/test/MC/Disassembler/Mips/octeonp/valid.txt
  llvm/test/MC/Mips/cnmipsp/invalid.s
  llvm/test/MC/Mips/cnmipsp/valid.s
  llvm/test/MC/Mips/elf_eflags.s
  llvm/test/MC/Mips/elf_header.s
  llvm/test/MC/Mips/macro-saa.s

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