[PATCH] D69392: [ARM] MVE interleaving load and stores.

[Dave Green via Phabricator via llvm-commits]

dmgreen marked an inline comment as done.
dmgreen added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp:817
+    if (ST->hasMVEIntegerOps() && Factor == 2 && NumElts / Factor > 2 &&
+        VecTy->isIntOrIntVectorTy() && DL.getTypeSizeInBits(SubVecTy) <= 128)
+      return 2 * BaseCost;
----------------
samparker wrote:
> if this is handling the smaller vector types, shouldn't this be <= 64 instead? Is the 2 below 'Factor'? If so it would be good to use the variable name or a clear explanation of what it is.
Oh, yeah, it's SrcVecTy, so yes <= 64 will be fine (128 will already be handled in the above if).

The 2 below is VLDR, VREV or VLDR; VMOVN. 2 Instructions though. I'll add a comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69392/new/

https://reviews.llvm.org/D69392