[llvm] 7d9af03 - [Scheduling][ARM] Consistently enable PostRA Machine scheduling
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 5 03:09:43 PST 2019
Author: David Green
Date: 2019-11-05T10:44:55Z
New Revision: 7d9af03ff7a0d4fb6ae3ec224a0d8d7398bdbd84
URL: https://github.com/llvm/llvm-project/commit/7d9af03ff7a0d4fb6ae3ec224a0d8d7398bdbd84
DIFF: https://github.com/llvm/llvm-project/commit/7d9af03ff7a0d4fb6ae3ec224a0d8d7398bdbd84.diff
LOG: [Scheduling][ARM] Consistently enable PostRA Machine scheduling
In the ARM backend, for historical reasons we have only some targets
using Machine Scheduling. The rest use the old list scheduler as they
are using itinaries and the list scheduler seems to produce better code
(and not crash running out of register on v6m codes). So whether to use
the MIScheduler or not is checked at runtime from the subtarget
features.
This is fine, except for post-ra scheduling. Whether to use the old
post-ra list scheduler or the post-ra machine schedule is decided as the
pass manager is set up, in arms case from a newly constructed subtarget.
Under some situations, like LTO, this won't include the correct cpu so
can pick the wrong option. This can have a surprising effect on
performance.
To fix that, this patch overrides targetSchedulesPostRAScheduling and
addPreSched2 in the ARM backend, adding _both_ post-ra schedulers and
picking at runtime which to execute. To pick between the two I've had to
add a enablePostRAMachineScheduler() method that normally returns
enableMachineScheduler() && enablePostRAScheduler(), which can be
overridden to enable just one of PostRAMachineScheduler vs
PostRAScheduler.
Thanks to David Penry for the identifying this problem.
Differential Revision: https://reviews.llvm.org/D69775
Added:
llvm/test/CodeGen/ARM/postrasched.ll
Modified:
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/TargetSubtargetInfo.cpp
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.h
llvm/test/CodeGen/ARM/O3-pipeline.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 56018eca8c27..6768cea89406 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -206,6 +206,10 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
/// which is the preferred way to influence this.
virtual bool enablePostRAScheduler() const;
+ /// True if the subtarget should run a machine scheduler after register
+ /// allocation.
+ virtual bool enablePostRAMachineScheduler() const;
+
/// True if the subtarget should run the atomic expansion pass.
virtual bool enableAtomicExpand() const;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index f0721ea3b76d..caebb9534390 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -402,7 +402,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (EnablePostRAMachineSched.getNumOccurrences()) {
if (!EnablePostRAMachineSched)
return false;
- } else if (!mf.getSubtarget().enablePostRAScheduler()) {
+ } else if (!mf.getSubtarget().enablePostRAMachineScheduler()) {
LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
return false;
}
diff --git a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
index 59eb2f9c88cb..63766df4d2be 100644
--- a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -54,6 +54,10 @@ bool TargetSubtargetInfo::enablePostRAScheduler() const {
return getSchedModel().PostRAScheduler;
}
+bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
+ return enableMachineScheduler() && enablePostRAScheduler();
+}
+
bool TargetSubtargetInfo::useAA() const {
return false;
}
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 09603057b2c8..c9316a71bdfa 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -381,9 +381,19 @@ bool ARMSubtarget::enableMachineScheduler() const {
// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool ARMSubtarget::enablePostRAScheduler() const {
+ if (enableMachineScheduler())
+ return false;
+ if (disablePostRAScheduler())
+ return false;
+ // Thumb1 cores will generally not benefit from post-ra scheduling
+ return !isThumb1Only();
+}
+
+bool ARMSubtarget::enablePostRAMachineScheduler() const {
+ if (!enableMachineScheduler())
+ return false;
if (disablePostRAScheduler())
return false;
- // Don't reschedule potential IT blocks.
return !isThumb1Only();
}
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index ef460342a69e..ad0b1bb5dee3 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -806,6 +806,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
/// True for some subtargets at > -O0.
bool enablePostRAScheduler() const override;
+ /// True for some subtargets at > -O0.
+ bool enablePostRAMachineScheduler() const override;
+
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool useAA() const override { return UseAA; }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7f85b93beac5..10f68542e7e1 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -322,14 +322,7 @@ namespace {
class ARMPassConfig : public TargetPassConfig {
public:
ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
- : TargetPassConfig(TM, PM) {
- if (TM.getOptLevel() != CodeGenOpt::None) {
- ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
- TM.getTargetFeatureString());
- if (STI.hasFeature(ARM::FeatureUseMISched))
- substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
- }
- }
+ : TargetPassConfig(TM, PM) {}
ARMBaseTargetMachine &getARMTargetMachine() const {
return getTM<ARMBaseTargetMachine>();
@@ -523,6 +516,13 @@ void ARMPassConfig::addPreSched2() {
}
addPass(createMVEVPTBlockPass());
addPass(createThumb2ITBlockPass());
+
+ // Add both scheduling passes to give the subtarget an opportunity to pick
+ // between them.
+ if (getOptLevel() != CodeGenOpt::None) {
+ addPass(&PostMachineSchedulerID);
+ addPass(&PostRASchedulerID);
+ }
}
void ARMPassConfig::addPreEmitPass() {
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index cb8650d8139b..ac55d2bdcc2b 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -70,6 +70,8 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
TargetTriple.isOSWindows() ||
TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
}
+
+ bool targetSchedulesPostRAScheduling() const override { return true; };
};
/// ARM/Thumb little endian target machine.
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index cb6a005445b7..dd741388d749 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -141,6 +141,7 @@
; CHECK-NEXT: Thumb IT blocks insertion pass
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
+; CHECK-NEXT: PostRA Machine Instruction Scheduler
; CHECK-NEXT: Post RA top-down list latency scheduler
; CHECK-NEXT: Analyze Machine Code For Garbage Collection
; CHECK-NEXT: Machine Block Frequency Analysis
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
index 2c0aa98eae03..be3df4aae506 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
;
@a = global i32 0, align 4
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
index 02d1c2f55f99..1835870850eb 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have LDM instruction combined from single-loads
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
index 67cddc14d047..2ee5f75bec3a 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
; CHECK: ********** MI Scheduling **********
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
index 474f39d84bae..026a62f35201 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; N=3 STMIB should have latency 2cyc
; CHECK: ********** MI Scheduling **********
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
index 1baf472ca49d..88b772cc294e 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
;
@a = global double 0.0, align 4
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
index 8da133e806ef..ac208c65af28 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have VLDM instruction combined from single-loads
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
index 05c498eee49f..c517f46e5614 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
index f31474f66558..5e9041ce0842 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
diff --git a/llvm/test/CodeGen/ARM/postrasched.ll b/llvm/test/CodeGen/ARM/postrasched.ll
new file mode 100644
index 000000000000..85593d55105c
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/postrasched.ll
@@ -0,0 +1,30 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -debug-only=machine-scheduler,post-RA-sched -print-before=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL: test_misched
+; Pre and post ra machine scheduling
+; CHECK: ********** MI Scheduling **********
+; CHECK: t2LDRi12
+; CHECK: Latency : 2
+; CHECK: ********** MI Scheduling **********
+; CHECK: t2LDRi12
+; CHECK: Latency : 2
+
+define i32 @test_misched(i32* %ptr) "target-cpu"="cortex-m33" {
+entry:
+ %l = load i32, i32* %ptr
+ store i32 0, i32* %ptr
+ ret i32 %l
+}
+
+; CHECK-LABEL: test_rasched
+; CHECK: Subtarget disables post-MI-sched.
+; CHECK: ********** List Scheduling **********
+
+define i32 @test_rasched(i32* %ptr) {
+entry:
+ %l = load i32, i32* %ptr
+ store i32 0, i32* %ptr
+ ret i32 %l
+}
+
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