[PATCH] D69443: [PowerPC] Test case for vector float gather on ppc64le and ppc64

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp requested changes to this revision.
stefanp added a comment.
This revision now requires changes to proceed.

Please make sure that your test does not put restrictions on the allocation of output registers. See my comments.
Otherwise I think this looks fine.



================
Comment at: llvm/test/CodeGen/PowerPC/float-vector-gather.ll:13
+float* nocapture readonly %d) {
+; C code from which this IR test case was generate:
+; vector float test(float *a, float *b, float *c, float *d) {
----------------
nit:
generate -> generated


================
Comment at: llvm/test/CodeGen/PowerPC/float-vector-gather.ll:23
+; CHECK-LE-DAG:    lfs f[[REG3:[0-9]+]], 0(r6)
+; CHECK-LE-DAG:    xxmrghd vs[[REG0]], vs[[REG2]], vs[[REG0]]
+; CHECK-LE-NEXT:   xvcvdpsp v[[VREG2:[0-9]+]], vs[[REG0]]
----------------
So `xxmrghd` computes the contents of one register based on the other two. 
`xxmrghd vs[[Newly Defined Output Register]], vs[[REG2]], vs[[REG0]]`
Nothing says that we need to allocate the same register for the output of `xxmrghd` as the output of `lfs`(REG0).


================
Comment at: llvm/test/CodeGen/PowerPC/float-vector-gather.ll:37
+; CHECK-BE-DAG:    xxmrghd vs[[REG0]], vs[[REG0]], vs[[REG2]]
+; CHECK-BE-DAG:    xxmrghd vs[[REG1]], vs[[REG1]], vs[[REG3]]
+; CHECK-BE-NEXT:   xvcvdpsp v[[VREG2:[0-9]+]], vs[[REG1]]
----------------
Same as above. The outputs of the two `xxmrghd` instructions don't need to be [[REG0]] or [[REG1]]. The register allocator may decide to use a different register there.


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https://reviews.llvm.org/D69443