[PATCH] D69513: [GlobalISel] Widen one type at the time for insert/extract vector elt

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added a comment.

> I don't understand the motivation. 
> The vector element and insert element type need to match, but it appears there's a missing verifier check

This is definitely true for llvm-ir `insertelement` and `extractvalue`.
But SDAG nodes `ISD::INSERT_VECTOR_ELT` and `ISD::EXTRACT_VECTOR_ELT` don't follow this,
Mips uses DAGTypeLegalizer::PromoteIntegerResult for i8 and i16 and promotes them to i32 leaving vector scalar type unchanged.
In .td file element being inserted/extracted has i32 operand type (for i8, i16 and i32) and instruction is selected based on vector type (v16i8, v8i16, v4i32).


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https://reviews.llvm.org/D69513