[PATCH] D69735: [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.

[Michael Liao via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
hliao marked an inline comment as done.
Closed by commit rG4531aee2ac16: [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`. (authored by hliao).

Changed prior to commit:
  https://reviews.llvm.org/D69735?vs=227521&id=227535#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69735/new/

https://reviews.llvm.org/D69735

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll


Index: llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
+++ llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
@@ -157,3 +157,14 @@
   %mul2 = mul i32 %mul0, %mul1
   ret i32 %mul2
 }
+
+; GFX9-LABEL: known_bits_mul24:
+; GFX9: v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    s_setpc_b64
+define i32 @known_bits_mul24() {
+  %r0 = call i32 @llvm.amdgcn.mul.i24(i32 0, i32 -7)
+  %r1 = shl i32 %r0, 2
+  ret i32 %r1
+}
+
+declare i32 @llvm.amdgcn.mul.i24(i32, i32)
Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4435,6 +4435,9 @@
     unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
                       RHSKnown.countMinTrailingZeros();
     Known.Zero.setLowBits(std::min(TrailZ, 32u));
+    // Skip extra check if all bits are known zeros.
+    if (TrailZ >= 32)
+      break;
 
     // Truncate to 24 bits.
     LHSKnown = LHSKnown.trunc(24);


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