[llvm] 3842b94 - Revert rG57ee0435bd47f23f3939f402914c231b4f65ca5e - [TII] Use optional destination and source pair as a return value; NFC
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 31 11:02:10 PDT 2019
Author: Simon Pilgrim
Date: 2019-10-31T18:00:29Z
New Revision: 3842b94c4e7292de5f9e368bd60c64fc084c1bbe
URL: https://github.com/llvm/llvm-project/commit/3842b94c4e7292de5f9e368bd60c64fc084c1bbe
DIFF: https://github.com/llvm/llvm-project/commit/3842b94c4e7292de5f9e368bd60c64fc084c1bbe.diff
LOG: Revert rG57ee0435bd47f23f3939f402914c231b4f65ca5e - [TII] Use optional destination and source pair as a return value; NFC
This is breaking MSVC builds: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/20375
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.h
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/lib/Target/Mips/MipsSEInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 09f4095124dc..66420c1c4184 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -64,11 +64,6 @@ template <class T> class SmallVectorImpl;
using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
-struct DestSourcePair {
- const MachineOperand &Destination;
- const MachineOperand &Source;
-};
-
//---------------------------------------------------------------------------
///
/// TargetInstrInfo - Interface to description of machine instruction set
@@ -923,36 +918,41 @@ class TargetInstrInfo : public MCInstrInfo {
}
protected:
- /// Target-dependent implementation for IsCopyInstr.
+ /// Target-dependent implemenation for IsCopyInstr.
/// If the specific machine instruction is a instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- virtual Optional<DestSourcePair>
- isCopyInstrImpl(const MachineInstr &MI) const {
- return None;
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ virtual bool isCopyInstrImpl(const MachineInstr &MI,
+ const MachineOperand *&Source,
+ const MachineOperand *&Destination) const {
+ return false;
}
public:
/// If the specific machine instruction is a instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- /// For COPY-instruction the method naturally returns destination and source
- /// registers as machine operands, for all other instructions the method calls
- /// target-dependent implementation.
- Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ /// For COPY-instruction the method naturally returns true, for all other
+ /// instructions the method calls target-dependent implementation.
+ bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const {
if (MI.isCopy()) {
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ Destination = &MI.getOperand(0);
+ Source = &MI.getOperand(1);
+ return true;
}
- return isCopyInstrImpl(MI);
+ return isCopyInstrImpl(MI, Source, Destination);
}
/// If the specific machine instruction is an instruction that adds an
- /// immediate value to its source operand and stores it in destination,
- /// return destination and source registers as machine operands along with
- /// \c Offset which has been added.
- virtual Optional<DestSourcePair> isAddImmediate(const MachineInstr &MI,
- int64_t &Offset) const {
- return None;
+ /// immediate value to its \c Source operand and stores it in \c Destination,
+ /// return true along with \c Destination and \c Source machine operand to
+ /// which \c Offset has been added.
+ virtual bool isAddImmediate(const MachineInstr &MI,
+ const MachineOperand *&Destination,
+ const MachineOperand *&Source,
+ int64_t &Offset) const {
+ return false;
}
/// Store the specified register of the given register class to the specified
diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp
index d38840b7d8ad..b15c594a4545 100644
--- a/llvm/lib/CodeGen/LiveDebugValues.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues.cpp
@@ -997,14 +997,10 @@ void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
OpenRangesSet &OpenRanges,
VarLocMap &VarLocIDs,
TransferMap &Transfers) {
+ const MachineOperand *SrcRegOp, *DestRegOp;
- auto DestSrc = TII->isCopyInstr(MI);
- if (!DestSrc)
- return;
-
- const MachineOperand &DestRegOp = DestSrc->Destination;
- const MachineOperand &SrcRegOp = DestSrc->Source;
- if (!SrcRegOp.isKill() || !DestRegOp.isDef())
+ if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
+ !DestRegOp->isDef())
return;
auto isCalleeSavedReg = [&](unsigned Reg) {
@@ -1014,8 +1010,8 @@ void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
return false;
};
- Register SrcReg = SrcRegOp.getReg();
- Register DestReg = DestRegOp.getReg();
+ Register SrcReg = SrcRegOp->getReg();
+ Register DestReg = DestRegOp->getReg();
// We want to recognize instructions where destination register is callee
// saved register. If register that could be clobbered by the call is
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index f5f53b50ab8c..88fbfcb7784b 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1124,13 +1124,14 @@ Optional<ParamLoadedValue>
TargetInstrInfo::describeLoadedValue(const MachineInstr &MI) const {
const MachineFunction *MF = MI.getMF();
DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
+ const MachineOperand *SrcRegOp, *DestRegOp;
int64_t Offset;
- if (auto DestSrc = isCopyInstr(MI)) {
- return ParamLoadedValue(DestSrc->Source, Expr);
- } else if (auto DestSrc = isAddImmediate(MI, Offset)) {
+ if (isCopyInstr(MI, SrcRegOp, DestRegOp)) {
+ return ParamLoadedValue(*SrcRegOp, Expr);
+ } else if (isAddImmediate(MI, DestRegOp, SrcRegOp, Offset)) {
Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
- return ParamLoadedValue(DestSrc->Source, Expr);
+ return ParamLoadedValue(*SrcRegOp, Expr);
}
return None;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c627ad4004b2..d6578e3f4f92 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5936,33 +5936,39 @@ bool AArch64InstrInfo::shouldOutlineFromFunctionByDefault(
return MF.getFunction().hasMinSize();
}
-Optional<DestSourcePair>
-AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isCopyInstrImpl(
+ const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const {
// AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
// and zero immediate operands used as an alias for mov instruction.
if (MI.getOpcode() == AArch64::ORRWrs &&
MI.getOperand(1).getReg() == AArch64::WZR &&
MI.getOperand(3).getImm() == 0x0) {
- return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
+ Destination = &MI.getOperand(0);
+ Source = &MI.getOperand(2);
+ return true;
}
if (MI.getOpcode() == AArch64::ORRXrs &&
MI.getOperand(1).getReg() == AArch64::XZR &&
MI.getOperand(3).getImm() == 0x0) {
- return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
+ Destination = &MI.getOperand(0);
+ Source = &MI.getOperand(2);
+ return true;
}
- return None;
+ return false;
}
-Optional<DestSourcePair>
-AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
- int64_t &Offset) const {
+bool AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
+ const MachineOperand *&Destination,
+ const MachineOperand *&Source,
+ int64_t &Offset) const {
int Sign = 1;
switch (MI.getOpcode()) {
default:
- return None;
+ return false;
case AArch64::SUBWri:
case AArch64::SUBXri:
case AArch64::SUBSWri:
@@ -5976,14 +5982,16 @@ AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
// TODO: Third operand can be global address (usually some string).
if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
!MI.getOperand(2).isImm())
- return None;
+ return false;
+ Source = &MI.getOperand(1);
Offset = MI.getOperand(2).getImm() * Sign;
int Shift = MI.getOperand(3).getImm();
assert((Shift == 0 || Shift == 12) && "Shift can be either 0 or 12");
Offset = Offset << Shift;
}
}
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ Destination = &MI.getOperand(0);
+ return true;
}
Optional<ParamLoadedValue>
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 11d2d7d74a21..ece791674689 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -265,8 +265,10 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
/// on Windows.
static bool isSEHInstruction(const MachineInstr &MI);
- Optional<DestSourcePair> isAddImmediate(const MachineInstr &MI,
- int64_t &Offset) const override;
+ bool isAddImmediate(const MachineInstr &MI,
+ const MachineOperand *&Destination,
+ const MachineOperand *&Source,
+ int64_t &Offset) const override;
Optional<ParamLoadedValue>
describeLoadedValue(const MachineInstr &MI) const override;
@@ -275,11 +277,11 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
#include "AArch64GenInstrInfo.inc"
protected:
- /// If the specific machine instruction is an instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- Optional<DestSourcePair>
- isCopyInstrImpl(const MachineInstr &MI) const override;
+ /// If the specific machine instruction is a instruction that moves/copies
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const override;
private:
/// Sets the offsets on outlined instructions in \p MBB which use SP
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 175532c63a05..ffc967769fea 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -993,8 +993,9 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Mov->addRegisterKilled(SrcReg, TRI);
}
-Optional<DestSourcePair>
-ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+bool ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
+ const MachineOperand *&Src,
+ const MachineOperand *&Dest) const {
// VMOVRRD is also a copy instruction but it requires
// special way of handling. It is more complex copy version
// and since that we are not considering it. For recognition
@@ -1005,8 +1006,10 @@ ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
if (!MI.isMoveReg() ||
(MI.getOpcode() == ARM::VORRq &&
MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
- return None;
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ return false;
+ Dest = &MI.getOperand(0);
+ Src = &MI.getOperand(1);
+ return true;
}
const MachineInstrBuilder &
@@ -5347,9 +5350,10 @@ ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
return makeArrayRef(TargetFlags);
}
-Optional<DestSourcePair>
-ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
- int64_t &Offset) const {
+bool ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
+ const MachineOperand *&Destination,
+ const MachineOperand *&Source,
+ int64_t &Offset) const {
int Sign = 1;
unsigned Opcode = MI.getOpcode();
@@ -5357,17 +5361,19 @@ ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
if (Opcode == ARM::SUBri)
Sign = -1;
else if (Opcode != ARM::ADDri)
- return None;
+ return false;
// TODO: Third operand can be global address (usually some string). Since
// strings can be relocated we cannot calculate their offsets for
// now.
if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
!MI.getOperand(2).isImm())
- return None;
+ return false;
+ Destination = &MI.getOperand(0);
+ Source = &MI.getOperand(1);
Offset = MI.getOperand(2).getImm() * Sign;
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ return true;
}
bool llvm::registerDefinedBetween(unsigned Reg,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 29c3f3a88e70..0f4f2d4b687d 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -99,11 +99,12 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
unsigned OpIdx1,
unsigned OpIdx2) const override;
- /// If the specific machine instruction is an instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- Optional<DestSourcePair>
- isCopyInstrImpl(const MachineInstr &MI) const override;
+
+ /// If the specific machine instruction is a instruction that moves/copies
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const override;
public:
// Return whether the target has an explicit NOP encoding.
@@ -455,8 +456,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
return MI.getOperand(3).getReg();
}
- Optional<DestSourcePair> isAddImmediate(const MachineInstr &MI,
- int64_t &Offset) const override;
+ bool isAddImmediate(const MachineInstr &MI,
+ const MachineOperand *&Destination,
+ const MachineOperand *&Source,
+ int64_t &Offset) const override;
};
/// Get the operands corresponding to the given \p Pred value. By default, the
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index e619b7055846..0d735c20ec2f 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -96,11 +96,15 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MIB.addReg(SrcReg, getKillRegState(KillSrc));
}
-Optional<DestSourcePair>
-Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
- if (MI.isMoveReg())
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
- return None;
+bool Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
+ const MachineOperand *&Src,
+ const MachineOperand *&Dest) const {
+ if (MI.isMoveReg()) {
+ Dest = &MI.getOperand(0);
+ Src = &MI.getOperand(1);
+ return true;
+ }
+ return false;
}
void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.h b/llvm/lib/Target/Mips/Mips16InstrInfo.h
index 6d16f08d354e..dadcaa3055b3 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.h
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.h
@@ -104,9 +104,10 @@ class Mips16InstrInfo : public MipsInstrInfo {
protected:
/// If the specific machine instruction is a instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- Optional<DestSourcePair> isCopyInstrImpl(const MachineInstr &MI) const override;
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const override;
private:
unsigned getAnalyzableBrOpc(unsigned Opc) const override;
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 30b8e22dd5f2..2126a1bda493 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -221,24 +221,29 @@ static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
/// We check for the common case of 'or', as it's MIPS' preferred instruction
/// for GPRs but we have to check the operands to ensure that is the case.
/// Other move instructions for MIPS are directly identifiable.
-Optional<DestSourcePair>
-MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+bool MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
+ const MachineOperand *&Src,
+ const MachineOperand *&Dest) const {
bool isDSPControlWrite = false;
// Condition is made to match the creation of WRDSP/RDDSP copy instruction
// from copyPhysReg function.
if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
- if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4))
- return None;
+ if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
+ return false;
else if (isDSPControlWrite) {
- return DestSourcePair{MI.getOperand(2), MI.getOperand(0)};
-
+ Src = &MI.getOperand(0);
+ Dest = &MI.getOperand(2);
} else {
- return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
+ Dest = &MI.getOperand(0);
+ Src = &MI.getOperand(2);
}
+ return true;
} else if (MI.isMoveReg() || isORCopyInst(MI)) {
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
+ Dest = &MI.getOperand(0);
+ Src = &MI.getOperand(1);
+ return true;
}
- return None;
+ return false;
}
void MipsSEInstrInfo::
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/llvm/lib/Target/Mips/MipsSEInstrInfo.h
index 76b32569fe41..3111d1c21a0a 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.h
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.h
@@ -77,10 +77,10 @@ class MipsSEInstrInfo : public MipsInstrInfo {
protected:
/// If the specific machine instruction is a instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- Optional<DestSourcePair>
- isCopyInstrImpl(const MachineInstr &MI) const override;
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const override;
private:
unsigned getAnalyzableBrOpc(unsigned Opc) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index be39a376f1f5..8fdcf1eec7c1 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3046,11 +3046,15 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
report_fatal_error("Cannot emit physreg copy instruction");
}
-Optional<DestSourcePair>
-X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
- if (MI.isMoveReg())
- return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
- return None;
+bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
+ const MachineOperand *&Src,
+ const MachineOperand *&Dest) const {
+ if (MI.isMoveReg()) {
+ Dest = &MI.getOperand(0);
+ Src = &MI.getOperand(1);
+ return true;
+ }
+ return false;
}
static unsigned getLoadStoreRegOpcode(unsigned Reg,
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 77043a59c8ba..22b7b1d4cb19 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -542,10 +542,10 @@ class X86InstrInfo final : public X86GenInstrInfo {
unsigned CommuteOpIdx2) const override;
/// If the specific machine instruction is a instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
- Optional<DestSourcePair>
- isCopyInstrImpl(const MachineInstr &MI) const override;
+ /// value from one register to another register return true along with
+ /// @Source machine operand and @Destination machine operand.
+ bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
+ const MachineOperand *&Destination) const override;
private:
/// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
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