[PATCH] D68996: [AArch64][SVE] Spilling/filling of SVE callee-saves.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen marked 6 inline comments as done.
sdesmalen added a comment.

In D68996#1727014 <https://reviews.llvm.org/D68996#1727014>, @ostannard wrote:

> I'd like to see some more tests for this, in particular:
>
> - Different combinations of register types being saved, e.g. only P regs without X or Z regs.
> - Check that pairing of other register types still works in the presence of SVE callee-saved registers.


Thanks for the review! I've added some new tests, please let me know if that satisfies your comment.



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Comment at: lib/Target/AArch64/AArch64MachineFunctionInfo.h:176
 
+  void setSVECalleeSavedStackSize(unsigned Size) {
+    SVECalleeSavedStackSize = Size;
----------------
ostannard wrote:
> This could do with a comment about what units this is in, I guess it needs to be multiplied by the actual vector length to get the number of bytes?
Correct, these are "scalable bytes" which means they will be scaled at runtime by `vscale`. SVE vectors are `vscale * 128bits` wide.


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