[PATCH] D69059: [SVE][AArch64] Adding patterns for while intrinsics

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1435
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-  defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege">;
-  defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt">;
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These instructions should not be removed. (This is also guarded by the assembler/disassembler tests)


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:3425
+  def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32, nxv4i1, op>;
+  def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64, nxv2i1, op>;
 }
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nit: Given that we chose to be explicit about adding the patterns (see https://reviews.llvm.org/D69128#1725072), it would be nice to do the same for these patterns.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69059/new/

https://reviews.llvm.org/D69059