[PATCH] D69637: AMDGPU: Disallow spill folding with m0 copies

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, dstuttard.
Herald added subscribers: hiraditya, kristof.beyls, t-tye, tpr, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

readlane and writelane instructions are not allowed to use m0 as the
data operand, so spilling them is tricky and would require an
intermediate SGPR to spill it. Constrain the virtual register class in
this caes to disallow the inline spiller from folding the m0 operand
directly into the spill instruction.

     

I copied this hack from AArch64 which has the same problem for $sp.


https://reviews.llvm.org/D69637

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D69637.227168.patch
Type: text/x-patch
Size: 5510 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191030/834bd9f8/attachment.bin>