[PATCH] D69609: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (Baseline)

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 30 06:41:51 PDT 2019


spatel added inline comments.


================
Comment at: llvm/test/CodeGen/MSP430/shift-amount-threshold.ll:147
+; select C, 16, 0 -> shl C, 4
+define i16 @testSiymplifySelectCC_1(i16 %a, i16 %b) {
+; CHECK-LABEL: testSiymplifySelectCC_1:
----------------
Test name got garbled.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69609/new/

https://reviews.llvm.org/D69609





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