[llvm] c1498e3 - [RISCV] Remove RA from reserved register to use as callee saved register

[Shiva Chen via llvm-commits]

Author: Shiva Chen
Date: 2019-10-29T11:32:16+08:00
New Revision: c1498e37abe6ff1f3e338551c1d94d294a7e5ac4

URL: https://github.com/llvm/llvm-project/commit/c1498e37abe6ff1f3e338551c1d94d294a7e5ac4
DIFF: https://github.com/llvm/llvm-project/commit/c1498e37abe6ff1f3e338551c1d94d294a7e5ac4.diff

LOG: [RISCV] Remove RA from reserved register to use as callee saved register

Remove RA from reserved register list, so we could use it as callee saved register

Differential Revision: https://reviews.llvm.org/D67698

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    llvm/test/CodeGen/RISCV/callee-saved-gprs.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 65a7e41a23d6..d4c65a0b22ba 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -77,7 +77,6 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   // Use markSuperRegs to ensure any register aliases are also reserved
   markSuperRegs(Reserved, RISCV::X0); // zero
-  markSuperRegs(Reserved, RISCV::X1); // ra
   markSuperRegs(Reserved, RISCV::X2); // sp
   markSuperRegs(Reserved, RISCV::X3); // gp
   markSuperRegs(Reserved, RISCV::X4); // tp

diff  --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index 3cfb58d1edcf..eb3a4468bb9d 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -28,21 +28,22 @@ define void @callee() nounwind {
 ; RV32I-LABEL: callee:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -80
-; RV32I-NEXT:    sw s0, 76(sp)
-; RV32I-NEXT:    sw s1, 72(sp)
-; RV32I-NEXT:    sw s2, 68(sp)
-; RV32I-NEXT:    sw s3, 64(sp)
-; RV32I-NEXT:    sw s4, 60(sp)
-; RV32I-NEXT:    sw s5, 56(sp)
-; RV32I-NEXT:    sw s6, 52(sp)
-; RV32I-NEXT:    sw s7, 48(sp)
-; RV32I-NEXT:    sw s8, 44(sp)
-; RV32I-NEXT:    sw s9, 40(sp)
-; RV32I-NEXT:    sw s10, 36(sp)
-; RV32I-NEXT:    sw s11, 32(sp)
+; RV32I-NEXT:    sw ra, 76(sp)
+; RV32I-NEXT:    sw s0, 72(sp)
+; RV32I-NEXT:    sw s1, 68(sp)
+; RV32I-NEXT:    sw s2, 64(sp)
+; RV32I-NEXT:    sw s3, 60(sp)
+; RV32I-NEXT:    sw s4, 56(sp)
+; RV32I-NEXT:    sw s5, 52(sp)
+; RV32I-NEXT:    sw s6, 48(sp)
+; RV32I-NEXT:    sw s7, 44(sp)
+; RV32I-NEXT:    sw s8, 40(sp)
+; RV32I-NEXT:    sw s9, 36(sp)
+; RV32I-NEXT:    sw s10, 32(sp)
+; RV32I-NEXT:    sw s11, 28(sp)
 ; RV32I-NEXT:    lui a0, %hi(var)
 ; RV32I-NEXT:    lw a1, %lo(var)(a0)
-; RV32I-NEXT:    sw a1, 28(sp)
+; RV32I-NEXT:    sw a1, 24(sp)
 ; RV32I-NEXT:    addi a2, a0, %lo(var)
 ;
 ; RV32I-WITH-FP-LABEL: callee:
@@ -70,21 +71,22 @@ define void @callee() nounwind {
 ; RV64I-LABEL: callee:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -144
-; RV64I-NEXT:    sd s0, 136(sp)
-; RV64I-NEXT:    sd s1, 128(sp)
-; RV64I-NEXT:    sd s2, 120(sp)
-; RV64I-NEXT:    sd s3, 112(sp)
-; RV64I-NEXT:    sd s4, 104(sp)
-; RV64I-NEXT:    sd s5, 96(sp)
-; RV64I-NEXT:    sd s6, 88(sp)
-; RV64I-NEXT:    sd s7, 80(sp)
-; RV64I-NEXT:    sd s8, 72(sp)
-; RV64I-NEXT:    sd s9, 64(sp)
-; RV64I-NEXT:    sd s10, 56(sp)
-; RV64I-NEXT:    sd s11, 48(sp)
+; RV64I-NEXT:    sd ra, 136(sp)
+; RV64I-NEXT:    sd s0, 128(sp)
+; RV64I-NEXT:    sd s1, 120(sp)
+; RV64I-NEXT:    sd s2, 112(sp)
+; RV64I-NEXT:    sd s3, 104(sp)
+; RV64I-NEXT:    sd s4, 96(sp)
+; RV64I-NEXT:    sd s5, 88(sp)
+; RV64I-NEXT:    sd s6, 80(sp)
+; RV64I-NEXT:    sd s7, 72(sp)
+; RV64I-NEXT:    sd s8, 64(sp)
+; RV64I-NEXT:    sd s9, 56(sp)
+; RV64I-NEXT:    sd s10, 48(sp)
+; RV64I-NEXT:    sd s11, 40(sp)
 ; RV64I-NEXT:    lui a0, %hi(var)
 ; RV64I-NEXT:    lw a1, %lo(var)(a0)
-; RV64I-NEXT:    sd a1, 40(sp)
+; RV64I-NEXT:    sd a1, 32(sp)
 ; RV64I-NEXT:    addi a2, a0, %lo(var)
 ;
 ; RV64I-WITH-FP-LABEL: callee: