[PATCH] D69275: Add constrained int->FP intrinsics

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

This probably needs tests that will lower to single instructions. E.g. `llvm.experimental.constrained.uitofp.v4f32.v4i32` should lower to a `cvtps2dq` on SSE2.

Maybe testing an AVX512VL target would be interesting too. They have really good support for different CVT variants.



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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1020
+                                    Node->getOperand(1).getValueType());
+    break;
   case ISD::SIGN_EXTEND_INREG: {
----------------
Should these be clustered with STRICT_LRINT/etc?


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2425
+      Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
     return Result;
   }
----------------
Nit-picky: does this preserve the rounding results and flags raised?

If the target doesn't support the itofp instruction, I'm not sure if we can do better anyway. Just wondering if anyone had thought this through...


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2944
+      LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_xINT_TO_FP node\n");
+      return true;
+    } else
----------------
Is the early return necessary here? It stands out from the surrounding code...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69275/new/

https://reviews.llvm.org/D69275