[PATCH] D69486: PowerPC: Fix SPE f64 VAARG handling.

[Justin Hibbits via Phabricator via llvm-commits]

jhibbits created this revision.
jhibbits added reviewers: nemanjai, hfinkel, joerg.
Herald added subscribers: llvm-commits, shchenz, jsji, kbarton, hiraditya.
Herald added a project: LLVM.

SPE follows soft-float ABI for doubles, including VAARG passing.  For
soft-float, doubles are bitcast to i64, but for SPE they are not, so we
need to perform GPR alignment explicitly for SPE f64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69486

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3058,7 +3058,7 @@
                                     VAListPtr, MachinePointerInfo(SV), MVT::i8);
   InChain = GprIndex.getValue(1);
 
-  if (VT == MVT::i64) {
+  if (VT == MVT::i64 || (hasSPE() && VT == MVT::f64)) {
     // Check if GprIndex is even
     SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
                                  DAG.getConstant(1, dl, MVT::i32));


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