[PATCH] D69483: [PowerPC]: Fix predicate handling with SPE

[Justin Hibbits via Phabricator via llvm-commits]

jhibbits created this revision.
jhibbits added reviewers: nemanjai, hfinkel, joerg.
Herald added subscribers: llvm-commits, shchenz, jsji, kbarton, hiraditya.
Herald added a project: LLVM.

SPE floating-point compare instructions only update the GT bit in the CR
field.  All predicates must therefore be reduced to GT/LE.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69483

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -5048,6 +5048,32 @@
       PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(4));
 
     SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
+
+    if (PPCSubTarget->hasSPE() &&
+        N->getOperand(2).getValueType().isFloatingPoint()) {
+      // For SPE instructions, the result is in GT bit of the CR
+      switch (CC) {
+        case ISD::SETOEQ:
+        case ISD::SETEQ:
+        case ISD::SETOLT:
+        case ISD::SETLT:
+        case ISD::SETOGT:
+        case ISD::SETGT:
+          PCC = PPC::PRED_GT;
+          break;
+        case ISD::SETUNE:
+        case ISD::SETNE:
+        case ISD::SETULE:
+        case ISD::SETLE:
+        case ISD::SETUGE:
+        case ISD::SETGE:
+          PCC = PPC::PRED_LE;
+          break;
+        default:
+          break;
+      }
+    }
+
     SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
                         N->getOperand(4), N->getOperand(0) };
     CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);


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