[llvm] 3dd0a89 - [X86] Add a check for SSE2 to the top of combineReductionToHorizontal.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2019-10-25T11:11:32-07:00
New Revision: 3dd0a896b6402c1abf5cb153a7769cb1bb52bb6e

URL: https://github.com/llvm/llvm-project/commit/3dd0a896b6402c1abf5cb153a7769cb1bb52bb6e
DIFF: https://github.com/llvm/llvm-project/commit/3dd0a896b6402c1abf5cb153a7769cb1bb52bb6e.diff

LOG: [X86] Add a check for SSE2 to the top of combineReductionToHorizontal.

Without this, we can create a PSADBW node that isn't legal.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9e6285845713..6fb870afdaa6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36266,6 +36266,10 @@ static SDValue combineReductionToHorizontal(SDNode *ExtElt, SelectionDAG &DAG,
                                             const X86Subtarget &Subtarget) {
   assert(ExtElt->getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unexpected caller");
 
+  // We need at least SSE2 to anything here.
+  if (!Subtarget.hasSSE2())
+    return SDValue();
+
   ISD::NodeType Opc;
   SDValue Rdx =
       DAG.matchBinOpReduction(ExtElt, Opc, {ISD::ADD, ISD::FADD}, true);