[PATCH] D69250: [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLE

[Victor Campos via Phabricator via llvm-commits]

vhscampos marked an inline comment as done.
vhscampos added a comment.

Added support for `__clsll` as requested.



================
Comment at: clang/lib/Headers/arm_acle.h:150
+__clsl(unsigned long __t) {
+#if __SIZEOF_LONG__ == 4
+  return __builtin_arm_cls(__t);
----------------
compnerd wrote:
> vhscampos wrote:
> > compnerd wrote:
> > > vhscampos wrote:
> > > > compnerd wrote:
> > > > > I don't see a pattern match for the `cls64` on ARM32, would that not fail to lower?
> > > > Yes. However, for now, I am not enabling support for `cls64` on ARM32 as it is not done yet.
> > > Is the difference not just the parameter type?  I think that implementing it should be a trivial change to the existing implementation.  Is there a reason that you are not implementing that?
> > At clang's side, yes, but not in the backend: Arm32 does not have a `cls` instruction, thus the CLS operations need to be custom lowered. In the `llvm.arm.cls(i32)` case, lowering is quite simple, and it's been included in this patch. For `llvm.arm.cls64(i64)`, on the other hand, it is not as trivial since it's necessary to break its logic into 32-bit instructions.
> > 
> > So the reason not to implement that (yet) is just to split work in two different efforts.
> Would it not be sufficient to do the top half (after a shift right of 32-bits), and if it is exactly 32, then do the bottom 32-bits, otherwise, you're done?
Sort of. How we interpret the bottom half depends on the value of the top half. I've added this custom lowering in the latest revision.


Repository:
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  https://reviews.llvm.org/D69250/new/

https://reviews.llvm.org/D69250