[PATCH] D69212: [RISCV] Sign-extend 32-bit integer inline assembly operands on RV64I

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I was not aware of that aside in the spec, which does indeed suggest this specific case should sign-extend, and I guess gives us a reason why this isn't a slippery slope. However, even if this is the case, I still feel code shouldn't be relying on this, simply because it's unclear (and perhaps surprising to those who don't know this particular note from the spec). One might perfectly reasonably assume that both signed and unsigned i32 types (in the original source) are zero-extended, or (probably the default position of people) that the signed type is sign-extended and the unsigned type is zero-extended (which would require passing the extension information through via the asm call instruction's operands).


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https://reviews.llvm.org/D69212