[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin marked an inline comment as done.
kmclaughlin added a comment.

In D68877#1717820 <https://reviews.llvm.org/D68877#1717820>, @dmgreen wrote:

> I'm not sure if there is support yet for vector selects in the SVE codegen?


There is not yet support for vector selects, so for this patch the intention was that any passthru which is not all zero or undef would result in a selection failure.
Do you think it would acceptable to handle different passthrus in a future patch which also implements vector selects for SVE?



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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:4753
+  let hasSideEffects = 1, hasNoSchedulingInfo = 1, mayLoad = 1 in {
+  def "" : Pseudo<(outs listty:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4)>;
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dmgreen wrote:
> Can you explain why is this pseudo is needed, exactly? I feel that using pseudos is often the wrong solution to a problem (it may be required here, I'm just sure why exactly).
> 
> We currently seem to generate ld1b (for example), over ldnf1b. Is there ever a time that we expect to generate a nf load?
The pseudo was a workaround that was added downstream for non-faulting loads, but it is not needed here.


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