[PATCH] D69267: [PowerPC] Fix lrint and llrint code generation

[Colin Samples via Phabricator via llvm-commits]

vddvss created this revision.
vddvss added reviewers: hfinkel, nemanjai, stefanp, jsji.
vddvss added a project: LLVM.
Herald added subscribers: llvm-commits, shchenz, MaskRay, kbarton, hiraditya, kristof.beyls.

This patch fixes an issue where, in certain instances, when compiling code using the lrint and llrint LLVM intrinsics, LLVM can incorrectly optimize a loop to use hardware loop counters.

In terms of background, r361875 added lrint and llrint intrinsics to LLVM; however, the series only added support for instructions for AArch64, so on PPC and other platforms ll/lrint was emitted as a function call. On PPC, the hardware loop transform pass assumed that since an intrinsic was used, the ctr register would not be clobbered, and a transformation of the loop to use hardware loop intrinsics was valid. The function call clobbered ctr, resulting in incorrect code generation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69267

Files:
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/test/CodeGen/PowerPC/llrint-ctr-crash.ll

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