[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Do we need separate schedule information for compressed and uncompressed instructions? I would assume that any sensible RVC implementation would decode the two to exactly the same control logic (other than for PC incrementing and the original instruction for `mtval`).


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https://reviews.llvm.org/D68685