[PATCH] D69182: [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.

Fri Oct 18 10:48:55 PDT 2019

arsenm added inline comments.

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Comment at: lib/Target/AMDGPU/SILowerI1Copies.cpp:552

   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB.phis()) {
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Can we just use RPO order instead?

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Comment at: test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.ll:55-63
+10:                                               ; preds = %4
+  %11 = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #1
+  %12 = getelementptr inbounds i8, i8 addrspace(4)* %11, i64 4
+  %13 = bitcast i8 addrspace(4)* %12 to i16 addrspace(4)*
+  %14 = load i16, i16 addrspace(4)* %13, align 4
+  %15 = getelementptr inbounds i8, i8 addrspace(4)* %11, i64 12
+  %16 = bitcast i8 addrspace(4)* %15 to i32 addrspace(4)*
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This test is a bit complicated, and should also not use anonymous values. You should be able to reduce it further 

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69182/new/

https://reviews.llvm.org/D69182