[PATCH] D69130: [RISCV] Implement the TargetLowering::getRegisterByName hook

[Luís Marques via Phabricator via llvm-commits]

luismarques marked 2 inline comments as done.
luismarques added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2894
+Register
+RISCVTargetLowering::getRegisterByName(const char *RegName, EVT VT,
+                                       const MachineFunction &MF) const {
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lenary wrote:
> I think you need to be using the Type information in `VT` to check the register we're returning has the expected width/type
> 
> For instance, `@llvm.register_read.i32("sp")` on RISC-V 64 should absolutely fail. The same `@llvm.register_read.i64("sp")` should succeed on 64-bit RISC-V. I don't know if this test is done by the `register_read` intrinsic lowering or has to be done in this code.
If the type doesn't match the lowering will fail, complaining about not knowing how to promote `READ_REGISTER`. The hook is never reached, so it's not possible to do such check at the hook.


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  https://reviews.llvm.org/D69130/new/

https://reviews.llvm.org/D69130