[llvm] r375175 - [AMDGPU] drop getIsFP td helper
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 17 14:46:56 PDT 2019
Author: rampitec
Date: Thu Oct 17 14:46:56 2019
New Revision: 375175
URL: http://llvm.org/viewvc/llvm-project?rev=375175&view=rev
Log:
[AMDGPU] drop getIsFP td helper
We already have isFloatType helper, and they are out of sync.
Drop one and merge the type list.
Differential Revision: https://reviews.llvm.org/D69138
Modified:
llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
Modified: llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td?rev=375175&r1=375174&r2=375175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td Thu Oct 17 14:46:56 2019
@@ -715,7 +715,7 @@ multiclass MUBUF_Pseudo_Atomics_NO_RTN <
RegisterClass vdataClass,
ValueType vdataType,
SDPatternOperator atomic,
- bit isFP = getIsFP<vdataType>.ret> {
+ bit isFP = isFloatType<vdataType>.ret> {
let FPAtomic = isFP in
def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass>,
MUBUFAddr64Table <0, NAME>;
@@ -739,7 +739,7 @@ multiclass MUBUF_Pseudo_Atomics_RTN <str
RegisterClass vdataClass,
ValueType vdataType,
SDPatternOperator atomic,
- bit isFP = getIsFP<vdataType>.ret> {
+ bit isFP = isFloatType<vdataType>.ret> {
let FPAtomic = isFP in
def _OFFSET_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
[(set vdataType:$vdata,
Modified: llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td?rev=375175&r1=375174&r2=375175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td Thu Oct 17 14:46:56 2019
@@ -270,7 +270,7 @@ multiclass FLAT_Atomic_Pseudo<
SDPatternOperator atomic = null_frag,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
- bit isFP = getIsFP<data_vt>.ret> {
+ bit isFP = isFloatType<data_vt>.ret> {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
(ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
@@ -300,7 +300,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_
SDPatternOperator atomic = null_frag,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
- bit isFP = getIsFP<data_vt>.ret> {
+ bit isFP = isFloatType<data_vt>.ret> {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
@@ -333,7 +333,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN
SDPatternOperator atomic = null_frag,
ValueType data_vt = vt,
RegisterClass data_rc = vdst_rc,
- bit isFP = getIsFP<data_vt>.ret> {
+ bit isFP = isFloatType<data_vt>.ret> {
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=375175&r1=375174&r2=375175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Thu Oct 17 14:46:56 2019
@@ -284,7 +284,9 @@ class isFloatType<ValueType SrcVT> {
!if(!eq(SrcVT.Value, f64.Value), 1,
!if(!eq(SrcVT.Value, v2f16.Value), 1,
!if(!eq(SrcVT.Value, v4f16.Value), 1,
- 0)))));
+ !if(!eq(SrcVT.Value, v2f32.Value), 1,
+ !if(!eq(SrcVT.Value, v2f64.Value), 1,
+ 0)))))));
}
class isIntType<ValueType SrcVT> {
@@ -1424,18 +1426,6 @@ class getVALUDstForVT<ValueType VT> {
VOPDstS64orS32)))); // else VT == i1
}
-// Returns true if VT is floating point.
-class getIsFP<ValueType VT> {
- bit ret = !if(!eq(VT.Value, f16.Value), 1,
- !if(!eq(VT.Value, v2f16.Value), 1,
- !if(!eq(VT.Value, v4f16.Value), 1,
- !if(!eq(VT.Value, f32.Value), 1,
- !if(!eq(VT.Value, v2f32.Value), 1,
- !if(!eq(VT.Value, f64.Value), 1,
- !if(!eq(VT.Value, v2f64.Value), 1,
- 0)))))));
-}
-
// Returns the register class to use for the destination of VOP[12C]
// instructions with SDWA extension
class getSDWADstForVT<ValueType VT> {
@@ -1447,7 +1437,7 @@ class getSDWADstForVT<ValueType VT> {
// Returns the register class to use for source 0 of VOP[12C]
// instructions for the given VT.
class getVOPSrc0ForVT<ValueType VT> {
- bit isFP = getIsFP<VT>.ret;
+ bit isFP = isFloatType<VT>.ret;
RegisterOperand ret =
!if(isFP,
@@ -1487,7 +1477,7 @@ class getVregSrcForVT<ValueType VT> {
}
class getSDWASrcForVT <ValueType VT> {
- bit isFP = getIsFP<VT>.ret;
+ bit isFP = isFloatType<VT>.ret;
RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32);
RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32);
RegisterOperand ret = !if(isFP, retFlt, retInt);
@@ -1496,7 +1486,7 @@ class getSDWASrcForVT <ValueType VT> {
// Returns the register class to use for sources of VOP3 instructions for the
// given VT.
class getVOP3SrcForVT<ValueType VT> {
- bit isFP = getIsFP<VT>.ret;
+ bit isFP = isFloatType<VT>.ret;
RegisterOperand ret =
!if(!eq(VT.Size, 128),
VSrc_128,
@@ -1543,7 +1533,7 @@ class isModifierType<ValueType SrcVT> {
// Return type of input modifiers operand for specified input operand
class getSrcMod <ValueType VT, bit EnableF32SrcMods> {
- bit isFP = getIsFP<VT>.ret;
+ bit isFP = isFloatType<VT>.ret;
bit isPacked = isPackedType<VT>.ret;
Operand ret = !if(!eq(VT.Size, 64),
!if(isFP, FP64InputMods, Int64InputMods),
@@ -1562,7 +1552,7 @@ class getOpSelMod <ValueType VT> {
// Return type of input modifiers operand specified input operand for DPP
class getSrcModExt <ValueType VT> {
- bit isFP = getIsFP<VT>.ret;
+ bit isFP = isFloatType<VT>.ret;
Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
}
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