[PATCH] D69128: [AArch64][SVE] Add patterns for some integer vector instructions

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr created this revision.
dancgr added reviewers: huntergr, rengolin, amehsan.
dancgr added a project: LLVM.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
dancgr edited the summary of this revision.

This is another follow up to https://reviews.llvm.org/D68098.

Add pattern matching for SVE vector instructions:

- add, sub, and, or, xor instructions
- sqadd, uqadd, sqsub, uqsub target-independent intrinsics
- bic intrinsics
- predicated add, sub, and sub intrinsics


Repository:
  rL LLVM

https://reviews.llvm.org/D69128

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-int-arith-pred.ll
  llvm/test/CodeGen/AArch64/sve-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-int-log.ll

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