[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

Is there a forwarding mechanism in  Rocket? If so, that can be added to make the model more accurate.



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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:73
+
+// 32-bit divides have worse case latency of 34 cycle
+def : WriteRes<WriteIDiv, [Rocket32UnitIMul]> { let Latency = 34; }
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I guess its input dependent. Probably better to take average case 17.
Is 'Rocket32UnitIMul]' intentional (i.e. Div using Mul instead of UnitDiv) ? 
 If DIV is not pipelined then please put ResourceCycle = ... , as well. 


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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:1
+//==- RISCVSchedRocket.td - Rocket Scheduling Definitions -*- tablegen -*-=//
+//
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lenary wrote:
> This should match the filename.
What are the main differences in terms of schedule between Rocket63 and . Looks like to me that a lot of code can be factored out into a common td


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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:92
+
+def : WriteRes<WriteLDB, [Rocket64UnitMem]> { let Latency = 3; }
+def : WriteRes<WriteLDH, [Rocket64UnitMem]> { let Latency = 3; }
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You could use let Latency = 2 in {  ... } to avoid repeating


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