[PATCH] D67158: [ARM] Begin adding IR intrinsics for MVE instructions.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham updated this revision to Diff 225038.
simon_tatham edited the summary of this revision.
simon_tatham added a comment.

Rewritten this patch to do all its jobs in the same reasonably
consistent way.

Also, I've replaced my `mkpred` function-oid with a system of
`MVEVectorVTInfo`, similar to the x86 system that @dmgreen pointed
out. I think it works out more nicely, for two reasons. Firstly, I can
make separate classes for vectors of signed and unsigned integers,
which MVE distinguishes even though LLVM IR doesn't. Secondly, I can
also have those info records contain bits and pieces that can be used
in the main instruction definition: the type suffix on the mnemonic
(`.s32` or `.f16` or whatever), and at least the _usual_ way that
vector types are represented in MVE instruction encodings. So now
every time I have to add an `MVEVectorVTInfo` as an extra template
parameter, I'll be able to remove a few existing ones that it makes
redundant, so the declarations shouldn't get too complicated.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67158/new/

https://reviews.llvm.org/D67158

Files:
  llvm/include/llvm/IR/IntrinsicsARM.td
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vcvt.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vminvq.ll

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