[PATCH] D67392: [ARM][ParallelDSP] Change smlad insertion order

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: lib/Target/ARM/ARMParallelDSP.cpp:379
+  for (auto Write : Writes) {
+    for (auto Read : Loads) {
       MemoryLocation ReadLoc =
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Just curious, why did you change the iteration order, Loads/Writes vs. Writes/Loads? 


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Comment at: test/CodeGen/ARM/ParallelDSP/blocks.ll:139
+; scalars.
+; CHECK-LABEL: num_load_limit
+; CHECK: call i32 @llvm.arm.smlad
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Double checking I understand this test: this test has 16 loads, so is within the limit of 16.
So why don't we generate the 4th SMLAD?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67392/new/

https://reviews.llvm.org/D67392