[PATCH] D68337: [ARM][MVE] Enable extending masked loads

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9308
+                                        ISD::NodeType ExtOpc) {
+  if (!TLI.isLoadExtLegal(ExtLoadType, VT, N0.getValueType()))
+    return SDValue();
----------------
Is this function missing a one use check?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9311
+
+  if (VT.isVector() && !TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
+    return SDValue();
----------------
Would a masked load ever not be a vector type?


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9318
+
+  SDLoc dl(Ld);
+  SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru());
----------------
What if the masked load is already an extending load?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68337/new/

https://reviews.llvm.org/D68337