[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

[Simon Cook via Phabricator via llvm-commits]

simoncook marked 2 inline comments as done.
simoncook added inline comments.


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Comment at: clang/include/clang/Driver/Options.td:2224
   HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
-foreach i = {1-7,9-15,18,20-28} in
-  def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group<m_aarch64_Features_Group>,
-    HelpText<"Reserve the "#i#" register (AArch64 only)">;
+foreach i = {1-31} in
+  def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group<m_Group>,
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luismarques wrote:
> Given the expansion of the flags here, the AArch64 driver should probably detect and reject the flags `-ffixed-x[8,16-17,19,29-31]`, to preserve the old behavior where passing those flags  would be an error and to ensure that erroneous flags are not silently accepted.
With this patch, for AArch64 using -ffixed-x8 for example will produce a warning that the flag is unused, similar to any other architecture trying to use these flags; I'll look at a follow-up patch that explicitly produces errors.


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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:53
     : RISCVGenSubtargetInfo(TT, CPU, FS),
+      UserReservedRegister(RISCV::NUM_TARGET_REGS),
       FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
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luismarques wrote:
> This includes more than the x0 - x31 registers. If the intent is to only allow reserving the GPRs then this should be tightened.
For now this only covers GPRs, but going forward I was going to follow up with one for floating point, since these should also be reservable if we match all of GCCs behaviour, where every register should be marked as reserved.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67185/new/

https://reviews.llvm.org/D67185