[PATCH] D68341: [AIX] TOC pseudo expansion for 64bit large + 64bit small + 32bit large modes

[Xiangling Liao via Phabricator via llvm-commits]

Xiangling_L marked 2 inline comments as done.
Xiangling_L added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll:23
+; LARGE:       lwz [[REG2:[0-9]+]], LC0 at l([[REG1]])
+; LARGE:       lwz [[REG3:[0-9]+]], 0([[REG2]])
+; LARGE:       addis [[REG4:[0-9]+]], LC1 at u(2)
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hubert.reinterpretcast wrote:
> Xiangling_L wrote:
> > hubert.reinterpretcast wrote:
> > > That the ordering and interleaving of the logical operations involved differ between the various cases seem to indicate that the test is already too complicated. Please reduce the test to use a single memory operand (e.g., store a constant or return the value read).
> > @sfertile I guess your original purpose of creating this testcase is to test if load from TOC works for both `load` and `store`?
> If that is indeed the intent, then the goal can be achieved with more tests that are simpler.
Thanks, I will update the testcase


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  https://reviews.llvm.org/D68341/new/

https://reviews.llvm.org/D68341