[PATCH] D68793: [System Model] [TTI] Add TTI interfaces for write-combining buffers

[David Greene via Phabricator via llvm-commits]

greened added a comment.

In D68793#1704266 <https://reviews.llvm.org/D68793#1704266>, @hfinkel wrote:

> How do you imagine that we'd use this? Do we need some kind of size to go along with this?


See the Intel optimization guide, section 3.6.9.

https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf

Basically, this information can be used to inform loop transformations as well as use of non-temporal instructions.  A write-combining buffer is not the same as a store buffer.  A write-combining buffer is always one cache line in size, so I don't think we need size information.


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