[PATCH] D66210: [RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:552
+
+  // RISCV::PseudoRET = 4 bytes.
+  unsigned FrameOverhead = 4;
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sorear wrote:
> Note that `jr <reg>` is a compressible instruction regardless of the register used.
Thanks, I'll try and incorporate this too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210