[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIFixSGPRCopies.cpp:815-816
+
+          // Check for trivially easy constant prop into one of the operands
+          // If this is the case then perform the operation now to resolve SGPR
+          // issue. If we don't do that here we will always insert a mov to m0
----------------
I'm working on a patch to stop reserving m0; I suspect this will avoid the need for the special case propagation


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D51932/new/

https://reviews.llvm.org/D51932