[PATCH] D68424: [tblgen] Add getOperatorAsDef() to Record

[Daniel Sanders via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4b7cabf1e16f: [tblgen] Add getOperatorAsDef() to Record (authored by dsanders).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68424/new/

https://reviews.llvm.org/D68424

Files:
  llvm/include/llvm/TableGen/Record.h
  llvm/lib/TableGen/Record.cpp
  llvm/utils/TableGen/AsmWriterEmitter.cpp
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp


Index: llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -411,12 +411,8 @@
   assert(SourceDag && "Missing 'Input' in compress pattern!");
   LLVM_DEBUG(dbgs() << "Input: " << *SourceDag << "\n");
 
-  DefInit *OpDef = dyn_cast<DefInit>(SourceDag->getOperator());
-  if (!OpDef)
-    PrintFatalError(Rec->getLoc(),
-                    Rec->getName() + " has unexpected operator type!");
   // Checking we are transforming from compressed to uncompressed instructions.
-  Record *Operator = OpDef->getDef();
+  Record *Operator = SourceDag->getOperatorAsDef(Rec->getLoc());
   if (!Operator->isSubClassOf("RVInst"))
     PrintFatalError(Rec->getLoc(), "Input instruction '" + Operator->getName() +
                                        "' is not a 32 bit wide instruction!");
@@ -428,12 +424,7 @@
   assert(DestDag && "Missing 'Output' in compress pattern!");
   LLVM_DEBUG(dbgs() << "Output: " << *DestDag << "\n");
 
-  DefInit *DestOpDef = dyn_cast<DefInit>(DestDag->getOperator());
-  if (!DestOpDef)
-    PrintFatalError(Rec->getLoc(),
-                    Rec->getName() + " has unexpected operator type!");
-
-  Record *DestOperator = DestOpDef->getDef();
+  Record *DestOperator = DestDag->getOperatorAsDef(Rec->getLoc());
   if (!DestOperator->isSubClassOf("RVInst16"))
     PrintFatalError(Rec->getLoc(), "Output instruction  '" +
                                        DestOperator->getName() +
Index: llvm/utils/TableGen/AsmWriterEmitter.cpp
===================================================================
--- llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -784,8 +784,7 @@
       continue; // Aliases with priority 0 are never emitted.
 
     const DagInit *DI = R->getValueAsDag("ResultInst");
-    const DefInit *Op = cast<DefInit>(DI->getOperator());
-    AliasMap[getQualifiedName(Op->getDef())].insert(
+    AliasMap[getQualifiedName(DI->getOperatorAsDef(R->getLoc()))].insert(
         std::make_pair(CodeGenInstAlias(R, Target), Priority));
   }
 
Index: llvm/lib/TableGen/Record.cpp
===================================================================
--- llvm/lib/TableGen/Record.cpp
+++ llvm/lib/TableGen/Record.cpp
@@ -1930,6 +1930,13 @@
   ProfileDagInit(ID, Val, ValName, makeArrayRef(getTrailingObjects<Init *>(), NumArgs), makeArrayRef(getTrailingObjects<StringInit *>(), NumArgNames));
 }
 
+Record *DagInit::getOperatorAsDef(ArrayRef<SMLoc> Loc) const {
+  if (DefInit *DefI = dyn_cast<DefInit>(Val))
+    return DefI->getDef();
+  PrintFatalError(Loc, "Expected record as operator");
+  return nullptr;
+}
+
 Init *DagInit::resolveReferences(Resolver &R) const {
   SmallVector<Init*, 8> NewArgs;
   NewArgs.reserve(arg_size());
Index: llvm/include/llvm/TableGen/Record.h
===================================================================
--- llvm/include/llvm/TableGen/Record.h
+++ llvm/include/llvm/TableGen/Record.h
@@ -1330,6 +1330,7 @@
   void Profile(FoldingSetNodeID &ID) const;
 
   Init *getOperator() const { return Val; }
+  Record *getOperatorAsDef(ArrayRef<SMLoc> Loc) const;
 
   StringInit *getName() const { return ValName; }
 


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