[PATCH] D67556: [ARM][AArch64][DebugInfo] Improve call site instruction interpretation

[Nikola Prica via Phabricator via llvm-commits]

NikolaPrica updated this revision to Diff 223848.
NikolaPrica added a comment.

-Include Destination operand in `isAddImmediate()`
-Exclude description of add immediate instructions where source and destination registers are the same.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67556/new/

https://reviews.llvm.org/D67556

Files:
  include/llvm/CodeGen/TargetInstrInfo.h
  lib/CodeGen/AsmPrinter/DwarfDebug.cpp
  lib/CodeGen/TargetInstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.h
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h
  test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
  test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D67556.223848.patch
Type: text/x-patch
Size: 27010 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191008/6df3ef15/attachment.bin>