[PATCH] D68232: [DAGCombine] Match a greater range of rotate when not all bits are demanded.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix marked an inline comment as done.
deadalnix added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6376
+  return MatchRotate(LHS, RHS, DL,
+                     APInt::getMaxValue(LHS.getValueType().getSizeInBits()));
+}
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RKSimon wrote:
> Shouldn't this be: APInt::getMaxValue(LHS.getScalarValueSizeInBits()) ?
> 
> TBH I'd prefer getAllOnesValue as well as it avoids the signed/unsigned ambiguity of getMaxValue.
That wouldn't generate the proper pattern for vectors and would leave things such as only the last element is demanded.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68232/new/

https://reviews.llvm.org/D68232