[PATCH] D67990: [aarch64] fix generation of fp16 fmls

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/fp16-fmla.ll:163
+; CHECK: fneg    {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK: fmla    {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
 entry:
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Why are we not generating a fmls?

And a nit, but perhaps actually just using registers v0, v1, and v2 here makes things clearer?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67990/new/

https://reviews.llvm.org/D67990