[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Haicheng Wu via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGaed6e52b3c3f: [AArch64] Coalesce Copy Zero during instruction selection (authored by haicheng).
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D36104?vs=134832&id=223511#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D36104/new/

https://reviews.llvm.org/D36104

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
  llvm/test/CodeGen/AArch64/arm64-cse.ll
  llvm/test/CodeGen/AArch64/copy-zero-reg.ll
  llvm/test/CodeGen/AArch64/i128-fast-isel-fallback.ll

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