[PATCH] D68563: [AMDGPU] Disable a test that was relying on misched behavior

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: arsenm, rampitec, vpykhtin, mareko.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.
Herald added a project: LLVM.

This test only passed because misched ordered the instructions in a way
that happened to work. With other orderings, register scavenging would
fail and llc would fail assertions or crash. I've demonstrated this by
disabling misched, which makes the test fail, and then disabling the
test itself.

I'm told that the SGPR spill to smem path was never fully completed, and
should probably be expected to be buggy.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68563

Files:
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr-spill-to-smem.ll


Index: llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr-spill-to-smem.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr-spill-to-smem.ll
+++ llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr-spill-to-smem.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=ALL %s
+; REQUIRES: disabled
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -enable-misched=false -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=ALL %s
 
 ; FIXME: SGPR-to-SMEM requires an additional SGPR always to scavenge m0
 


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