[llvm] r373740 - [AMDGPU][MC][GFX10] Enabled decoding of 'null' operand

[Dmitry Preobrazhensky via llvm-commits]

Author: dpreobra
Date: Fri Oct  4 05:38:36 2019
New Revision: 373740

URL: http://llvm.org/viewvc/llvm-project?rev=373740&view=rev
Log:
[AMDGPU][MC][GFX10] Enabled decoding of 'null' operand

See bug 43485: https://bugs.llvm.org/show_bug.cgi?id=43485

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D68348

Added:
    llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
Modified:
    llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=373740&r1=373739&r2=373740&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Fri Oct  4 05:38:36 2019
@@ -1095,6 +1095,7 @@ MCOperand AMDGPUDisassembler::decodeSpec
   case 106: return createRegOperand(VCC);
   case 108: return createRegOperand(TBA);
   case 110: return createRegOperand(TMA);
+  case 125: return createRegOperand(SGPR_NULL);
   case 126: return createRegOperand(EXEC);
   case 235: return createRegOperand(SRC_SHARED_BASE);
   case 236: return createRegOperand(SRC_SHARED_LIMIT);

Added: llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt?rev=373740&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt Fri Oct  4 05:38:36 2019
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
+
+# GFX10: s_ashr_i64 s[0:1], null, s0     ; encoding: [0x7d,0x00,0x80,0x91]
+0x7d,0x00,0x80,0x91
+
+# GFX10: s_and_b64 s[0:1], null, null    ; encoding: [0x7d,0x7d,0x80,0x87]
+0x7d,0x7d,0x80,0x87